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mp6004 primary-side regulated flyback/buck 80v dcdc converter mp6004 rev. 1.0 www.monolithicpower.com 1 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. the future of analog ic technology description the mp6004 is a monolithic flyback dc-dc converter with a 180 v power switch that targets isolated or non-isolated 13 w poe applications. it supports both primary-side regulated flyback and high-voltage buck applications. mp6004 uses fixed peak current and variable frequency discontinuous conduction mode (dcm) to regulate constant output voltage. the primary-side regulation without opto-coupler feedback in flyback mode simplifies the design and saves bom cost while buck mode minimizes the solution size for non-isolated applications. a 180 v integrated power mosfet optimizes the device for various wide voltage applications. the mp6004 protection features include over- load protection, over-voltage protection, open- circuit protection, and thermal shutdown. the mp6004 is available in a qfn-14 3mm x 3mm package. features ? supports primary-side regulated flyback without opto-coupler feedback ? supports buck from up to 80 v input ? integrated 180 v switching power mosfet ? internal 80 v start-up circuit ? up to 3 a programmable current limit ? discontinuous conduction mode ? olp, ovp, open-circuit, and thermal protection ? flexible self-power or external v cc power ? minimal external component count ? available in a qfn-14 3mm x 3mm package applications ? security cameras ? voip phones ? wlan access points ? general flyback and buck converters all mps parts are lead-free, halogen-free, and adhere to the rohs directive. fo r mps green status, please visit the mps website under qualit y assurance. ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application
mp6004?primary-side regulated flyback/buck 80v dcdc converter mp6004 rev. 1.0 www.monolithicpower.com 2 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. ordering information part number* package top marking MP6004GQ qfn-14 (3mm x 3mm) see below * for tape & reel, add suffix ?z (e.g. MP6004GQ?z) top marking amn: product code of MP6004GQ y: year code lll: lot number package reference top view
mp6004?primary-side regulated flyback/buck 80v dcdc converter mp6004 rev. 1.0 www.monolithicpower.com 3 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. absolute maxi mum ratings (1) vin ............................................-0.3 v to +100 v sw ............................................-0.7 v to +180 v fb1 .........................................-0.7 v to +6.5 v (2) fb2 to vin .................................-6.5 v to +0.3 v all other pins ...........................-0.3 v to +6.5 v (3) vcc sinking current ............................. 1.5 ma (4) fb1 sinking current ............................... 1 ma (2) en sinking current .................................. 1 ma (5) continuous power dissipation (t a = +25c) (6) ................................................................ 2.5 w junction temperature ................................150 c lead temperature .....................................260 c storage temperature ................ -65 c to +150 c recommended operating conditions (7) supply voltage (v in ) ........................14 v to 80 v switching voltage (v sw ) ............-0.5 v to +150 v maximum vcc sinking current ............ 1.2 ma (4) maximum fb1 sinking current ........... 0.5 ma (2) maximum en sinking current ............... 0.5 ma (5) maximum switching frequency.............. 200 khz maximum current limit................................... 3 a switching junction temp. (t j ). .. -40c to +125c thermal resistance (8) ja jc qfn-14 (3mm x 3mm)........... 50....... 12 c/w notes: 1) exceeding these ratings may damage the device. 2) refer to the ?output voltage setting? section on page 18. 3) vcc and en voltage can be pulled higher than this rating, but the external pull-up current should be limited. refer to ?vcc sinking current? and ?en sinki ng current? ratings to the left. 4) refer to the ?v cc power supply setting? section on page 17.. 5) refer to the ?en control setting? section on page 17. 6) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction - to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max) = (t j (max)-t a )/ ja . exceeding the maximum allowable powe r dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 7) the device is not guaranteed to function outside of its operating conditions. 8) measured on jesd51-7, 4-layer pcb.
mp6004?primary-side regulated flyback/buck 80v dcdc converter mp6004 rev. 1.0 www.monolithicpower.com 4 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. electrical characteristics v in = 48 v, v en = 5 v, v out = 12 v, t j = -40c to 125c, typical value is tested at 25c, unless otherwise noted. parameter symbol condition min typ max units power supply and uvlo vin uvlo rising threshold v in-r v in rising 10.5 11.6 12.8 v vin uvlo falling threshold v in-f v in falling 7.4 8.2 9 v vcc regulation (9) v cc load = 0 ma to 10 ma 4.8 5.4 5.9 v vcc uvlo rising threshold (9) v cc-r v in is higher than uvlo, vcc rising 4.3 4.7 5.1 v vcc uvlo falling threshold (9) v cc-f v in is higher than uvlo, vcc falling 4 4.5 4.8 v quiescent current i q v fb1 = 2.2 v, v fb2 = v in 380 a en high-level voltage 3.9 v en low-level voltage 1.3 v en input current 5.5 7.5 a voltage feedback respect to gnd, t j = 25c 1.94 1.99 2.04 v fb1 reference voltage v ref1 respect to gnd, t j = -40c to +125c 1.93 1.99 2.05 v fb1 leakage current i fb1 respect to gnd, v fb1 = 2 v 10 50 na flyback mode dcm detect threshold on fb1 v dcm1 respect to gnd 25 50 75 mv fb1 open-circuit threshold v fb1open -90 -60 -20 mv fb1 ovp threshold v fb1ovp 120% 125% 130% v ref1 minimum diode conduction time for fb1 sample t sample 1.4 2.2 3 s respect to v in , t j = 25c -1.955 -1.88 -1.805 v fb2 reference voltage v ref2 respect to v in , t j = -40c to +125c -1.96 -1.88 -1.8 v fb2 leakage current i fb2 respect to v in , v fb2 = -2 v 10 50 na buck mode dcm detect threshold on sw v dcm2 respect to v in 0 0.14 v switching power device on resistance r on-sw v cc = 5.4 v 0.8 ? current sense current limit i limit r ilim = 53.6 k?, l = 47 h 1.85 2.05 2.25 a current leading-edge blanking time t leb 450 ns
mp6004?primary-side regulated flyback/buck 80v dcdc converter mp6004 rev. 1.0 www.monolithicpower.com 5 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. electrical characteristics (continued) v in = 48 v, v en = 5 v, v out = 12 v, t j = -40c to 125c, typical value is tested at 25c, unless otherwise noted. parameter symbol condition min typ max units dcdc converter thermal shutdown thermal shutdown temperature (10) t sd 150 oc thermal shutdown hysteresis (10) t hys 20 oc notes: 9) the maximum vcc uvlo rising threshold is higher than the minimum vcc regulation in the ec table due to production distributi on. however, for one unit, vcc regulation is higher than the vcc uvlo rising threshold. t he vcc uvlo rising threshold is about 87 p ercent of the vcc regulation voltage, and the vcc uvlo falling threshol d is about 83 percent of the vcc regulation voltage in one unit . 10) guaranteed by characterization, not tested in production.
mp6004?primary-side regulated flyback/buck 80v dcdc converter mp6004 rev. 1.0 www.monolithicpower.com 6 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. typical performanc e characteristics v in = 48 v, v out = 12 v, i out = 1 a, t a = 25c, unless otherwise noted.
mp6004?primary-side regulated flyback/buck 80v dcdc converter mp6004 rev. 1.0 www.monolithicpower.com 7 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. typical performanc e characteristics (continued) v in = 48 v, v out = 12 v, i out = 1 a, t a = 25c, unless otherwise noted.
mp6004?primary-side regulated flyback/buck 80v dcdc converter mp6004 rev. 1.0 www.monolithicpower.com 8 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. typical performanc e characteristics (continued) v in = 48 v, v out = 12 v, i out = 1 a, flyback mode, t a = 25c, unless otherwise noted.
mp6004?primary-side regulated flyback/buck 80v dcdc converter mp6004 rev. 1.0 www.monolithicpower.com 9 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. typical performanc e characteristics (continued) v in = 48 v, v out = 12 v, i out = 1 a, flyback mode, t a = 25c, unless otherwise noted.
mp6004?primary-side regulated flyback/buck 80v dcdc converter mp6004 rev. 1.0 www.monolithicpower.com 10 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. typical performanc e characteristics (continued) v in = 48 v, v out = 12 v, i out = 1 a, flyback mode, t a = 25c, unless otherwise noted.
mp6004?primary-side regulated flyback/buck 80v dcdc converter mp6004 rev. 1.0 www.monolithicpower.com 11 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. typical performanc e characteristics (continued) v in = 48 v, v out = 12 v, i out = 1 a, flyback mode, t a = 25c, unless otherwise noted.
mp6004?primary-side regulated flyback/buck 80v dcdc converter mp6004 rev. 1.0 www.monolithicpower.com 12 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. pin functions pin# name description 1, 2 gnd switching converter power return . 3 en regulator on/off control input. en can program vin uvlo start-up through a zener diode and a resistor divider. 4,12 nc no connection. nc is not connected internally. float nc or connect to gnd in layout. 5 vin positive power supply terminal. 6 fb2 feedback for non-isolated buck solution. connect fb2 to vin in flyback application. 7 mode buck mode or flyback mode select pin. mode is pulled up internally to vcc through a 1.5 a current source. float mode for buck application mode; connect mode to gnd for flyback application mode. 8 fb1 feedback for flyback solution. connect fb1 to gnd in buck application. 9 ilim ic switching current limit program pin. connect ilim to gnd through a resistor to program the peak current limit. 10 agnd analog power return for switching converter control circuit. 11 vcc supply bias voltage pin, powered through internal ldo from vin . it is recommended to connect a capacitor (no less than 1 f) between vcc and gnd. 13,14 sw drain of converter switching mosfet.
mp6004?primary-side regulated flyback/buck 80v dcdc converter mp6004 rev. 1.0 www.monolithicpower.com 13 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. function diagram high-voltage ldo vcc sw current sense gnd control & driver management fb1 dcm detection protection feedback sampling fb2 agnd ilim ilimit program mode vin vin/vcc uvlo en vin v aux v aux vin vin vout figure 1?functional block diagram
mp6004?primary-side regulated flyback/buck 80v dcdc converter mp6004 rev. 1.0 www.monolithicpower.com 14 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. operation start-up and power supply mp6004 features an 80 v start-up circuit. when v in is higher than 4.3 v, the capacitor at vcc is charged through the internal ldo. normally v cc is regulated at 5.4 v (if vin is high enough), and the v cc uvlo is 4.7 v, typically. with the exception of v cc uvlo, the mp6004 has an additional 11.6 v v in uvlo. when v in is higher than the 11.6 v uvlo, v cc is charged higher than the 4.7 v uvlo, and en pin is high, mp6004 starts switching. v cc can be powered from the transformer auxiliary winding to save ic power loss. refer to the ?vcc power supply setting? section on page 18 for more details. flyback and buck mode mp6004 supports both flyback and buck topology applications. connect mode to gnd to set the mp6004 in flyback mode, and float mode to set the mp6004 in buck mode. mode is pulled up internally to v cc through a 1.5 a current source. do not connect mode to v in in buck mode, and do not place a resistor between mode and gnd in flyback mode. switching work principle after start-up, mp6004 works in discontinuous conduction mode (dcm). the second switching cycle will not start until the inductor current drops to 0 a. in each cycle, the internal mosfet is turned on, and the current-sense circuit senses the current i p(t) internally. use equation (1) to calculate the rate at which the current rises linearly in flyback mode: p(t) in m di v dt l = (1) when i p(t) rises up to i pk , the internal mosfet turns off (see figure 2). the energy stored in the primary-side inductance transfers to the secondary-side through the transformer. figure 2?primary-side current waveform the primary-side inductance (l m ) stores energy in each cycle as a function of equation (2): 2 mpk 1 eli 2 = (2) calculate the power transferred from the input to the output with equation (3): 2 mpk s 1 plif 2 = (3) where f s is the switching frequency. when i pk is constant, the output power depends on f s and l m . use equation (4) to calculate the rate at which the current rises linearly in buck mode: p(t) in out m di vv dt l ? = (4) the internal mosfet turns off when i p(t) rises to i pk (see figure 3). the output current is calculated with equation (5): out pk 1 idi 2 = (5) where, d is the inductor current conducting duty cycle. figure 3?inductor current waveform
mp6004?primary-side regulated flyback/buck 80v dcdc converter mp6004 rev. 1.0 www.monolithicpower.com 15 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. light-load control in flyback mode (if the load decreases), mp6004 stretches down the frequency automatically to reduce the power transferring while keeping the same i pk in each cycle. an approximate 10 khz minimum frequency is applied to detect the output voltage even at a very light load. during this condition, the switching i pk jumps between 20 percent of the normal i pk and 100 percent of the normal i pk to reduce the power transferring. the mp6004 still transfers some energy to the output even if there is no load on the output due to the 10 khz minimum frequency. this means that some load is required to maintain the output voltage, or else v out will rise and trigger an ovp. in buck mode, the mp6004 has no minimum frequency limit, so it stretches down to a very low frequency and regulates the output automatically even there is no load on the output. frequency control by monitoring the auxiliary winding voltage in flyback mode or monitoring the sw voltage in buck mode, the mp6004 detects and regulates the inductor current in dcm. the frequency is controlled by the peak current, the current ramp slew rate, and the load current. the maximum frequency occurs when the mp6004 runs in critical conduction mode, providing the maximum load power. the mp6004 switching frequency should be lower than 200 khz in the design. voltage control in flyback application, the mp6004 detects the auxiliary winding voltage from fb1 during the secondary-side diode conduction period. assume the secondary winding is the master, and the auxiliary winding is the slave. when the secondary-side diode conducts, the fb1 voltage is calculated with equation (6): a2 fb1 out d1f s12 nr v(vv) nr r = + + (6) where: v d1f is the output diode forward-drop voltage. v out is the output voltage. n a and n s are the turns of the auxiliary winding and the secondary-side winding, respectively. r1 and r2 are the resistor dividers for sampling. the output voltage differs from the secondary- winding voltage due to the current-dependant diode forward voltage drop. if the secondary- winding voltage is always detected at a fixed secondary current, the difference between the output voltage and the secondary-winding voltage is a fixed v d1f . mp6004 starts sampling the auxiliary-winding voltage after the internal power mosfet turns off for 0.7 s and finishes the sampling after the secondary-side diode conducts for 3 s. this provides good regulation when the load changes. however, the secondary diode conducting period must be longer than 3 s in each cycle, and the fb1 signal must be smooth 0.7 s after the switch turns off. with a buck solution, there is one fb2 pin referenced to vin. it can be used as the reference voltage for the buck application. the output voltage is referenced to vin and does not have the same gnd as the input power. programming the current limit the mp6004 current limit is set by an external resistor (r3) from ilim to ground. the value of r3 can be estimated with equation (7): l lim v0.18 100 i r3 l =+ (7) where i lim is the current limit in a, v l is the voltage applied on the inductor when the mosfet turns on, r3 is the setting resistor in k ? , and l is the inductor in h. the current limit cannot be programmed higher than 3 a. leading-edge blanking transformer parasitic capacitance induces a current spike on the sense resistor when the power switch turns on. the mp6004 includes a 450 ns leading-edge blanking period to avoid falsely terminating the switching pulse. during this blanking period, the current sense comparator is disabled, and the gate driver cannot switch off.
mp6004?primary-side regulated flyback/buck 80v dcdc converter mp6004 rev. 1.0 www.monolithicpower.com 16 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. dcm detection the mp6004 regulator operates in discontinuous conduction mode in both flyback and buck modes. in flyback mode, the mp6004 detects the falling edge of the fb1 voltage in each cycle. the second cycle switching will not start unless the chip detects a 50 mv falling edge on fb1. in buck mode, the mp6004 detects the falling edge of the sw voltage in each cycle. the second cycle switching will not start unless the chip detects 0.14 v falling edge between v sw -v in . over-voltage & open-circuit protection in flyback mode, the mp6004 includes over- voltage protection (ovp) and open-circuit protection. if the voltage at fb1 exceeds 125 percent of v ref1 (or fb1?s -60 mv falling edge cannot be detected because the feedback resistor is removed), immediately the mp6004 shuts off the driving signal and enters hiccup mode by re-charging the internal capacitor. the mp6004 resumes normal operation when the fault is removed. in buck mode, if the voltage at fb2 is higher than the reference voltage, the mp6004 stops switching immediately. over-load protection mp6004 will always work in dcm mode for any condition. in flyback mode, the secondary-side diode conduction duty cycle is limited to about 80 percent. in an over-load condition, the output energy is limited by i pk and f s . with a heavier load, the output drops and the diode conduction period becomes longer. this causes the switching frequency to drop so that the output energy can be limited. the mp6004 has same protection logic for an over-load/output-short condition. in buck mode, the duty cycle limitation does not apply, but the output current is limited to half of i pk . thermal shutdown when the junction temperature exceeds 150c, the mp6004 shuts down. once the temperature drops below 130c, the part re-starts automatically.
mp6004?primary-side regulated flyback/buck 80v dcdc converter mp6004 rev. 1.0 www.monolithicpower.com 17 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. application information en control setting mp6004 turns on when en goes high, and it turns off when en goes low. en is pulled low internally by an approximate 0.9 m ? resistor. in flyback mode, the maximum on time is limited at about 8 s. the secondary-side rectifier diode conduction time should be longer than 3 s for fb1 feedback sampling. if v in decreases and the inductor current cannot ramp the i pk to setting value within the maximum on time, the diode conduction time decreases to less than 3 s, causing fb1 feedback sample failure. the mp6004 treats this failure as a v out drop and generates more pulses, causing v out to overshoot. in this condition, en can be used to program v in uvlo and shuts down the part before v in drops (triggering the maximum on time). since the en high-level voltage is 3.9 v and the low-level voltage is 1.3 v, it is hard to program the v in uvlo with a small hysteresis. in this condition, one resistor divider and one zener diode is recommended (see figure 4). figure 4?vin uvlo setting with en control for example, the mp6004 should be turned on before v in rises to 36 v and shut down before v in drops to 20 v. one 20 v zener diode (d4) and a resistor divider (r5 = 100 k ? /r6 = 49.9 k ? ) can be selected to program the v in uvlo. the programmed v in rising threshold can be calculated with equation (8): in_r 100k 49.9k v 20v 3.9v 31.7v 49.9k + <+ = (8) the programmed v in falling threshold is calculated with equation (9): in_f 100k 49.9k v 20v 1.3v 23.9v 49.9k + >+ = (9) in buck mode, fb2 feedback is not affected by the rectifier diode conduction time, but the zener diode and resistor divider are recommended to set the appropriate v in uvlo. there is an internal zener diode on en, which clamps the en voltage to prevent runaway. the maximum pull-up current for the internal zener clamp (assuming 6.5 v) should be less than 0.5 ma. if en is driven with an external signal, use a signal voltage less than 6.5 v or connect en to the signal through a pull-up resistor that ensures the maximum pull-up current is less than 0.5 ma. if using a resistor divider (see figure 4) and v in -v zener is higher than 6.5 v, the minimum resistance for the pull-up resistor r5 should be calculated with equation (10): in zener vv 6.5v 6.5v 0.5ma r5 r6 ?? ?< (10) v cc power supply setting the v cc voltage is charged through the internal ldo by vin. normally, v cc is regulated at 5.4 v, typically. a capacitor no less than 1 f is recommended for decoupling between v cc and gnd. in flyback mode, v cc can be powered from the transformer auxiliary winding to save the high- voltage ldo power loss. figure 5?supply v cc from auxiliary winding the auxiliary winding supply voltage can be calculated with equation (11): a cc out d1f d3f s n v(vv)v n = + ? (11) where n a and n s are the turns of the auxiliary winding and the output winding, v d1f is the output rectifier diode voltage drop, and v d3f is the d3 voltage drop in figure 5. v cc voltage is clamped at about 6.2 v by one internal zener diode. the clamp current
mp6004?primary-side regulated flyback/buck 80v dcdc converter mp6004 rev. 1.0 www.monolithicpower.com 18 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. capability is about 1.2 ma. if the auxiliary winding power voltage is higher than 6.2 v (especially in a heavy-load condition), a series resistor (r8) is necessary to limit the current to vcc. for simple application, supply the v cc power through the internal ldo directly. output voltage setting in mp6004, there are two feedback pins for different application modes. in flyback mode, the converter detects the auxiliary winding voltage from fb1. r1 and r2 are the resistor dividers for the feedback sampling (see figure 6). gnd fb1 na r1 r2 figure 6?feedback in isolation application when the primary-side power mosfet turns off, the auxiliary-winding voltage is sampled. the output voltage is estimated with equation (12): s ref1 1 2 out d1f 2a n v(rr) vv rn + = ? (12) where, n s is the transformer secondary-side winding turns. n a is the transformer auxiliary winding turns. v d1f is the rectifier diode forward drop. v ref1 is the reference voltage of fb1 (1.99 v, typically). when the primary-side power mosfet turns on, the auxiliary winding forces a negative voltage to fb1. the fb1 voltage is clamped to less than -0.7 v internally, but the clamp current should be limited to less than -0.5 ma by r1. for example, if the auxiliary winding forces -11 v to r1 (to make the current flowing from fb1 to r1 lower than -0.5 ma), r1 resistance must be higher than 22 k ? (if ignoring r2 current). generally, select r2 with a 10 k ? to 50 k ? resistor to limit noise and provide an appropriate r1 for the -0.5 ma negative current limit. in buck application, the feedback pin is fb2. the output voltage can be estimated with equation (13): 12 out ref2 2 rr vv r + =? (13) where, v ref2 is the reference voltage of fb2 -1.88 v, typically. maximum switching frequency when mp6004 works in dcm, the frequency reaches its maximum value during a full-load condition. the maximum frequency is affected by the peak current limit, the inductance, and the input/output voltage. generally, design the maximum frequency lower than 200 khz. in buck mode, the maximum frequency occurs when the buck runs in critical conduction mode. the frequency can be calculated with equation (14): in out out sw _ max lim in (v v ) v f ilv ? = (14) where, i lim is the i pk set by the current limit resistor. with a lighter load, the frequency is lower than the maximum frequency above. in flyback mode, design the maximum frequency with the minimum input voltage and the maximum load condition. calculate the frequency with equation (15): sw on con delay 1 f tt t ++ (15) where: t on is the mosfet one pulse turn-on time determined with equation (16): lim m on in il t v = (16) l m is the transformer primary-winding inductance.
mp6004?primary-side regulated flyback/buck 80v dcdc converter mp6004 rev. 1.0 www.monolithicpower.com 19 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. t con is the rectifier diode current conducting time and can be calculated with equation (17): slim m con poutd1f ni l t n(v v) = + (17) where, n s is the transformer secondary-side winding turns.n p is the transformer primary-side winding turns. t delay is the resonant delay time from the rectifier diode current drop to 0 a to the auxiliary-winding voltage drop to 0 v. the resonant time can be tested on the board (estimate around 0.5 s). in flyback mode, the mp6004 samples the feedback signal within 3 s after the primary- side mosfet turns off. the secondary-side diode conduction time in equation (17) should be higher than 3 s. this time period, combined with the duty cycle, determines the maximum frequency. input capacitor selection an input capacitor is required to supply the ac ripple current to the inductor while limiting noise at the input source. a low esr capacitor is required to keep the noise to the ic at a minimum. ceramic capacitors are preferred, but tantalum or low esr electrolytic capacitors will suffice. for ceramic capacitors, the capacitance dominates the impedance at the switching frequency. the ripple will be the worst at light load. the required input capacitance can be estimated with equation (18): lim on 1 inp _ p 0.5 i t c v = (18) where c 1 is the input capacitor value, v inp-p is the expected input ripple, and t on is the mosfet turn-on time. in an isolated application, t on is calculated with equation (19): lim m on in il t v = (19) in a non-isolation application, t on is calculated with equation (20): lim on in out il t vv = ? (20) where l is the buck`s inductor value. output capacitor selection the output capacitor maintains the dc output voltage. for best results, use ceramic capacitors or low esr capacitors to minimize the output voltage ripple. for ceramic capacitors, the capacitance dominates the impedance at the switching frequency. in flyback application, the worst output ripple occurs under a light-load condition; the worst output ripple can be estimated by equation (21): plim con outp _ p s 0.5 n i t v nc2 = (21) where, c2 is the output capacitor value. v outp-p is the output ripple. normally, a 44 f or higher ceramic capacitor is recommended as the output capacitor. this allows a small vo ripple and stable operation. in buck application, the worst vout ripple can be estimated with equation (22): 2 lim in d1f outp _ p in out out d1f 0.5 i l (v v ) v c2 (v v ) (v v ) + = ? + (22) leakage inductance the transformer?s leakage inductance decreases system efficiency and affects the output current and voltage precision. optimize the transformer structure to minimize the leakage inductance. aim for a leakage inductance less than 3 percent of the primary- winding inductance. rcd snubber for flyback the transformer leakage inductance causes spikes and excessive ringing on the mosfet drain voltage waveform, affecting the output voltage sampling 0.7 s after the mosfet turns off. the rcd snubber circuit limits the sw voltage spike (see figure 7). figure 7?rcd snubber
mp6004?primary-side regulated flyback/buck 80v dcdc converter mp6004 rev. 1.0 www.monolithicpower.com 20 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. the power dissipation in the snubber circuit is estimated with equation (23): 2 sn k lim s 1 plif 2 = (23) where, l k is the leakage inductance. since r4 consumes the majority of the power, r4 is estimated with equation (24): 2 sn sn v r4 p = (24) where, v sn is the expected snubber voltage on c4. the snubber capacitor c4 can be designed to get appropriate voltage ripple on the snubber using equation (25): sn sn s v v r4 c4 f = (25) generally, a 15 percent ripple is acceptable. buck inductor selection the inductor is required to transfer the energy between the input source and the output capacitors. unlike normal application where inductors determine the inductor ripple, the mp6004 always works in dcm while v in , v out, and i lim are constant. the inductor only determines the speed of the current rising and falling, which determines the switching period. the expected maximum frequency can determine the inductor value using equation (26): in out out d1f in d1f peak sw (v v ) (v v ) 1 l (v v ) i f ?+ ? + (26) f sw is the expected maximum switching frequency, which should be lower than 200 khz in general setting. output diode selection the output rectifier diode supplies current to the output capacitor when the internal mosfet is off. use a schottky diode to reduce loss due to the diode forward voltage and recovery time. in isolation application, the diode should be rated for a reverse voltage greater than equation (27): in s d1 out pd1 p vn vv v n =+ + (27) v pd1 can be selected at 40 percent ~100 percent of v out + v in x n s /n p . an rc or rcd snubber circuit for the output diode d1 is recommended. in buck mode, the diode reverse voltage equates to the input voltage. a 20 percent ~ 40 percent margin is recommended. in both applications, the current rating should be higher than the maximum output current. dummy load when the system operates without a load in flyback mode, the output voltage rises above the normal operation voltage because of the minimum switching frequency limitation. use a dummy load for good load regulation. a large dummy load decreases efficiency, so the dummy load is a tradeoff between efficiency and load regulation. for applications using figure 10, a minimum load of around 10 ma is recommended. pcb layout guidelines efficient pcb layout for high-frequency switching power supplies is critical. poor layout may result in reduced performance, excessive emi, resistive loss, and system instability. for best results, refer to figure 8 and figure 9 and follow the guidelines below: for flyback application: 1. keep the input loop as short as possible between the input capacitor, transformer, sw, and gnd plane for minimal noise and ringing. 2. keep the output loop between the rectifier diode, the output capacitor, and the transformer as short as possible. 3. keep the clamp loop circuit between d2, c4, and the transformer as small as possible. 4. place the vcc capacitor close to vcc for the best decoupling. the current setting resistor r3 should be placed as close to ilim and agnd as possible. 5. keep the feedback trace far away from noise sources (such as sw). the trace connecting fb1 should be short.
mp6004?primary-side regulated flyback/buck 80v dcdc converter mp6004 rev. 1.0 www.monolithicpower.com 21 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. 6. use a single point connection between power gnd and signal gnd. vias around gnd and the thermal pad are recommended to lower the die temperature. figure 8?recommended flyback layout for buck application: 1. keep the input loop as short as possible between the input capacitor, rectifier diode, sw, and gnd plane for minimal noise and ringing. 2. keep the output loop between the rectifier diode, the output capacitor, and the inductor as short as possible. 3. place the vcc capacitor close to vcc for the best decoupling. the current setting resistor r3 should be placed as close to ilim and agnd as possible. 4. connect the output voltage sense and vin power supply from the output capacitor with parallel traces. the feedback trace should be far away from noise sources (such as sw). the trace connected to fb2 should be short. 5. use a single point connection between power gnd and signal gnd. vias around gnd and the thermal pad are recommended to lower the die temperature. 1 2 1 2 1 2 top layer bottom layer via vin vingnd vout voutgnd figure 9?recommended buck layout design example table 1 shows a design example following the application guidelines for the following specifications in flyback applications: table 1?flyback design example v in 36 v-72 v v out 12 v i out 0 a-1 a the typical application circuit for v out = 12 v in figure 10 shows the detailed application schematic and is the basis for the typical performance waveforms. for more detailed device applications, please refer to the related evaluation board datasheet. table 2 shows a design example following the application guidelines for the following specifications in buck applications: ta ble 2?buck design example v in 36 v-72 v v out 12 v i out 0 a-1 a the typical application circuit is shown in figure 11. for more detailed device applications, please refer to the related evaluation board datasheet.
mp6004?primary-side regulated flyback/buck 80v dcdc converter mp6004 rev. 1.0 www.monolithicpower.com 22 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. typical application circuits pgnd pgnd pgnd pgnd 12 v@1 a 2.2 f c1a 49.9 k r6 100 k r5 200 v d2 pgnd pgnd agnd 36 v-72 v vout 1 f c3 1nf/2000 v c6 np2 np1 ns t1 220 f c2c vin vin fb2 ilim mode fb1 sw gnd agnd vcc en u1 mp6004 pgnd 56.2 k r1 20 k r2 sbr8u60p5 d1 22 f c2a agnd 52.3 k r3 pgnd agnd 20 r7 1 nf c5 22 f c2b vcc vcc d3 47 f c1b 10 k r4 10 nf c4 1 k r8 voutgnd vingnd 20 v d4 figure 10?flyback application circuit, v in = 36 v-72 v, v out = 12 v, i out =1 a vin fb2 figure 11?buck application circuit, v in = 36 v-72 v, v out = 12 v, i out = 1 a 2.2 f 49.9 k 100 k 1 f 100 f ilim mode fb1 sw gnd agnd vcc en mp6004 20 k 33 k 22 f 43.2 k 47 f 10 h l1 gnd gnd gnd gnd gnd gnd 20 v figure 12?buck application circuit, v in = 36 v-72 v, v out = 5 v, i out = 1 a
mp6004?primary-side regulated flyback/buck 80v dcdc converter notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. mp6004 rev. 1.0 www.monolithicpower.com 23 4/14/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. package information qfn-14 (3mm x 3mm) side view bottom view note: 1) all dimensions are in millimeters. 2) exposed paddle size does not include mold flash. 3) lead coplanarity shall be 0.10 millimeters max. 4) jedec reference is mo-229. 5) drawing is not to scale. pin 1 id marking top view pin 1 id index area recommended land pattern pin 1 id see detail a pin 1 id option a 0.30x45 typ. pin 1 id option b r0.20 typ. detail a

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